{"created":"2023-07-25T10:24:26.696721+00:00","id":1761,"links":{},"metadata":{"_buckets":{"deposit":"c6c7d93a-43c5-45ab-b700-77b45370dcee"},"_deposit":{"created_by":1,"id":"1761","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"1761"},"status":"published"},"_oai":{"id":"oai:hiroshima-cu.repo.nii.ac.jp:00001761","sets":["54:383:402"]},"author_link":["10106","10109","10110","10105","10108","10111","10107","10104"],"item_3_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2000-08-03"},"bibliographicIssueNumber":"74","bibliographicPageEnd":"126","bibliographicPageStart":"121","bibliographicVolumeNumber":"2000","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告. 計算機アーキテクチャ研究会報告"}]}]},"item_3_description_19":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_3_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"並列処理環境の性能を引き出す上で問題となる様々なレイテンシ隠蔽し, かつ移植性のあるプログラムを記述することは重要である.この実現方法の1つとして細粒度並列処理がある.しかしながら, 細粒度並列処理を従来のOSを用いて実行するには問題がある.何故なら, 細粒度になるに従いコンテキスト・スイッチやスケジューリングの回数が増えるため, それらに起因するオーバヘッドが増加し, 大幅な性能低下を招く危険性があるためである.そこで, 本稿ではスケジューリング支援ハードウェア(Scheduling Support Hardware;SSH)を用いたマルチプロセッサ・アーキテクチャを提案する.これは, OSの機能の一部である, スレッドのスケジューリング, CPU資源の割り当て/解放の機能をハードウェアで支援することで, 細粒度な並列性を有効利用し, かつ高速なコンテキスト・スイッチやスケジューリングの実現を目指すものである.また, 本稿では, Verilog-HDLにてSSHを用いたマルチプロセッサを設計し, シミュレーションにより性能評価を行っている. ","subitem_description_type":"Abstract"},{"subitem_description":"This paper proposes a methodology in order to exploit fine grain parallelism effectively by introducing the scheduling support hardware(SSH). It is important to make a program that exploits the full hardware performance, and also has portability among different multiprocessor architectures on the same time. Although order to hide various types of latency, most tuned programs, that exploit high performance of the multiprocessor architecture, depend on its hardware architecture. Fine grain parallelism, in which a program is decomposed into many fine grain threads for parallel execution, is one solution for this problem. Fine grain parallelism achieves high performance, but it has a problem. As the grain becomes finer, scheduling and context switching are needed more frequently, which may affect the performance. This paper proposes the multiprocessor systems with scheduling support hardware to reduce above scheduling overhead. This paper describes its details and performance evaluation by simulation with Verilog-HDL.","subitem_description_type":"Abstract"}]},"item_3_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会"}]},"item_3_relation_12":{"attribute_name":"論文ID（NAID）","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"110002774869","subitem_relation_type_select":"NAID"}}]},"item_3_relation_17":{"attribute_name":"関連サイト","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"情報処理学会"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.ipsj.or.jp/","subitem_relation_type_select":"URI"}}]},"item_3_rights_15":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"ここに掲載した著作物の利用に関する注意：本著作物の著作権は（社）情報処理学会に帰属します。本著作物は著作権者である情報処理学会の許可のもとに掲載するものです。ご利用に当たっては「著作権法」ならびに「情報処理学会倫理綱領」に従うことをお願いいたします。 "},{"subitem_rights":"The copyright of this material is retained by the Information Processing Society of Japan (IPSJ). This material is published on this web site with the agreement of the author (s) and the IPSJ. Please be complied with Copyright Law of Japan and the Code of Ethics of the IPSJ if any users wish to reproduce, make derivative work, distribute or make available to the public any part or whole thereof. All Rights Reserved, Copyright (C) Information Processing Society of Japan."},{"subitem_rights":"本文データは学協会の許諾に基づきCiNiiから複製したものである。"}]},"item_3_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_3_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0919-6072","subitem_source_identifier_type":"ISSN"}]},"item_3_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐々木, 敬泰"},{"creatorName":"ササキ, タカヒロ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西村, 直己"},{"creatorName":"ニシムラ, ナオキ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"弘中, 哲夫"},{"creatorName":"ヒロナカ, テツオ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉田, 典可"},{"creatorName":"ヨシダ, ノリヨシ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"SASAKI, Takahiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"NISHIMURA, Naoki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"HIRONAKA, Tetsuo","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"YOSHIDA, Noriyoshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2023-05-26"}],"displaytype":"detail","filename":"110002774869.pdf","filesize":[{"value":"506.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"110002774869.pdf","url":"https://hiroshima-cu.repo.nii.ac.jp/record/1761/files/110002774869.pdf"},"version_id":"55ab61a9-4929-4df9-8bd7-4e4ebbc405c7"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"technical report","resourceuri":"http://purl.org/coar/resource_type/c_18gh"}]},"item_title":"マルチプロセッサ・システムに於けるスケジューリング支援ハードウェアのシミュレーション評価","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチプロセッサ・システムに於けるスケジューリング支援ハードウェアのシミュレーション評価"},{"subitem_title":"Scheduling Support Hardware for Multiprocessor System and its Evaluations","subitem_title_language":"en"}]},"item_type_id":"3","owner":"1","path":["402"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-05-26"},"publish_date":"2023-05-26","publish_status":"0","recid":"1761","relation_version_is_last":true,"title":["マルチプロセッサ・システムに於けるスケジューリング支援ハードウェアのシミュレーション評価"],"weko_creator_id":"1","weko_shared_id":1},"updated":"2023-07-25T10:33:03.366340+00:00"}