{"created":"2023-07-25T10:24:26.479094+00:00","id":1758,"links":{},"metadata":{"_buckets":{"deposit":"fc3e3142-5003-41f0-9ea7-5a584ff818e0"},"_deposit":{"created_by":1,"id":"1758","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"1758"},"status":"published"},"_oai":{"id":"oai:hiroshima-cu.repo.nii.ac.jp:00001758","sets":["54:383:402"]},"author_link":["10087","10086","10089","10084","10088","10082","10083","10085"],"item_3_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1997-08-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"76","bibliographicPageEnd":"96","bibliographicPageStart":"91","bibliographicVolumeNumber":"97","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告. 計算機アーキテクチャ研究会報告"}]}]},"item_3_description_19":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_3_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"近年, プロセッサとDRAMを1つのLSI上に混載することでメモリバンド幅を広げる研究が行われている. しかし, この方法ではベクトル処理的な用途以外では得られるメモリバンド幅を有効に活用できず, On Chip Multiprocessorなどの共有メモリとして利用しにくい. そこで我々はこの問題を解決するメモリ・アーキテクチャとして, FDUMAマルチポートメモリシステムを提案している. 本稿では, 現在開発中であるFDUMAメモリシステムの試作機で用いるバス・アービトレーションについて述べ, その後ソフトウェア・シミュレータによるFDUMAメモリシステムの特性評価を行う. ","subitem_description_type":"Abstract"},{"subitem_description":"Many research are done on deriving high memory bandwidth by merging the DRAM and logic on one chip. This merged DRAM/logic chip is effective for vector-style processing. Although it is not suitable for shared memory archtecture like the On Chip Multiprocessor. We proposes an memory archtecture, FDUMA Multiport Memory System, to solve the problem. This paper describes the method of bus arbitrations, that we use to impliment the prototype FDUMA Memory System. The results of performance evaluation done by software simulation are also presented.","subitem_description_type":"Abstract"}]},"item_3_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会"}]},"item_3_relation_12":{"attribute_name":"論文ID（NAID）","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"110002774714","subitem_relation_type_select":"NAID"}}]},"item_3_relation_17":{"attribute_name":"関連サイト","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"情報処理学会"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.ipsj.or.jp/","subitem_relation_type_select":"URI"}}]},"item_3_rights_15":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"ここに掲載した著作物の利用に関する注意：本著作物の著作権は（社）情報処理学会に帰属します。本著作物は著作権者である情報処理学会の許可のもとに掲載するものです。ご利用に当たっては「著作権法」ならびに「情報処理学会倫理綱領」に従うことをお願いいたします。  "},{"subitem_rights":"The copyright of this material is retained by the Information Processing Society of Japan (IPSJ). This material is published on this web site with the agreement of the author (s) and the IPSJ. Please be complied with Copyright Law of Japan and the Code of Ethics of the IPSJ if any users wish to reproduce, make derivative work, distribute or make available to the public any part or whole thereof. All Rights Reserved, Copyright (C) Information Processing Society of Japan."},{"subitem_rights":"本文データは学協会の許諾に基づきCiNiiから複製したものである。"}]},"item_3_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_3_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0919-6072","subitem_source_identifier_type":"ISSN"}]},"item_3_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"森垣, 利彦"},{"creatorName":"モリガキ, トシヒコ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"10082","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"弘中, 哲夫"},{"creatorName":"ヒロナカ, テツオ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"10083","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"児島, 彰"},{"creatorName":"コジマ, アキラ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"10084","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"藤野, 清次"},{"creatorName":"フジノ, セイジ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"10085","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"MORIGAKI, Toshihiko","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"10086","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"HIRONAKA, Tetsuo","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"10087","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"KOJIMA, Akira","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"10088","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"FUJINO, Seiji","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"10089","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2023-05-26"}],"displaytype":"detail","filename":"110002774714.pdf","filesize":[{"value":"562.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"110002774714.pdf","url":"https://hiroshima-cu.repo.nii.ac.jp/record/1758/files/110002774714.pdf"},"version_id":"87d899ff-611b-4d30-ae39-ed6b3b9aac2d"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"technical report","resourceuri":"http://purl.org/coar/resource_type/c_18gh"}]},"item_title":"FDUMA共有メモリ・アーキテクチャにおけるバス・アービトレーション","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FDUMA共有メモリ・アーキテクチャにおけるバス・アービトレーション"},{"subitem_title":"Bus Arbitration for FDUMA Shared Memory Architecture","subitem_title_language":"en"}]},"item_type_id":"3","owner":"1","path":["402"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-05-26"},"publish_date":"2023-05-26","publish_status":"0","recid":"1758","relation_version_is_last":true,"title":["FDUMA共有メモリ・アーキテクチャにおけるバス・アービトレーション"],"weko_creator_id":"1","weko_shared_id":1},"updated":"2023-07-25T10:33:07.670671+00:00"}