{"created":"2023-07-25T10:23:59.636963+00:00","id":1298,"links":{},"metadata":{"_buckets":{"deposit":"277eda74-b7f6-4d09-b79c-ddc1cf7b652f"},"_deposit":{"created_by":1,"id":"1298","owners":[1],"pid":{"revision_id":0,"type":"depid","value":"1298"},"status":"published"},"_oai":{"id":"oai:hiroshima-cu.repo.nii.ac.jp:00001298","sets":["1:210"]},"author_link":["4456","4457","4455","4458","4459"],"item_10001_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1997-10-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicPageEnd":"1833","bibliographicPageStart":"1826","bibliographicVolumeNumber":"E80-A","bibliographic_titles":[{"bibliographic_title":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"}]}]},"item_10001_description_19":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_10001_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a <>Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory (\"Harvard architecture\") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a \"defective\" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor \"ASAP-O\" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.","subitem_description_type":"Abstract"}]},"item_10001_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会(IEICE)"}]},"item_10001_relation_17":{"attribute_name":"関連サイト","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"http://www.ieice.org/jpn/trans_online/index.html"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.ieice.org/jpn/trans_online/index.html","subitem_relation_type_select":"URI"}}]},"item_10001_rights_15":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"copyright©1997IEICE"}]},"item_10001_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826239","subitem_source_identifier_type":"NCID"}]},"item_10001_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0916-8508","subitem_source_identifier_type":"ISSN"}]},"item_10001_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"OCHI, Hiroyuki"},{"creatorName":"オチ, ヒロユキ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"4455","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"KAMIDOI, Yoko"},{"creatorName":"カミドイ, ヨウコ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"4456","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"KAWABATA, Hideyuki"},{"creatorName":"カワバタ, ヒデユキ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"4457","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"上土井, 陽子","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"4458","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"川端, 英之","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"4459","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2023-02-28"}],"displaytype":"detail","filename":"E80-A_10 _1826.pdf","filesize":[{"value":"1.0 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"E80-A_10 _1826.pdf","url":"https://hiroshima-cu.repo.nii.ac.jp/record/1298/files/E80-A_10 _1826.pdf"},"version_id":"27eb1715-77c4-4eac-89af-2ee6d368968c"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"education of computer architecture","subitem_subject_scheme":"Other"},{"subitem_subject":"system design","subitem_subject_scheme":"Other"},{"subitem_subject":"DLX-like pipelined RISC processor","subitem_subject_scheme":"Other"},{"subitem_subject":"field-programmable gate array","subitem_subject_scheme":"Other"},{"subitem_subject":"verilog-HDL","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design"}]},"item_type_id":"10001","owner":"1","path":["210"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-02-28"},"publish_date":"2023-02-28","publish_status":"0","recid":"1298","relation_version_is_last":true,"title":["ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-07-25T10:48:02.012124+00:00"}