| Item type |
学術雑誌論文 / Journal Article(1) |
| 公開日 |
2023-02-28 |
| タイトル |
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|
タイトル |
ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design |
| 言語 |
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|
言語 |
eng |
| キーワード |
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|
主題 |
education of computer architecture |
| キーワード |
|
|
主題 |
system design |
| キーワード |
|
|
主題 |
DLX-like pipelined RISC processor |
| キーワード |
|
|
主題 |
field-programmable gate array |
| キーワード |
|
|
主題 |
verilog-HDL |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 著者 |
OCHI, Hiroyuki
KAMIDOI, Yoko
KAWABATA, Hideyuki
上土井, 陽子
川端, 英之
|
| 抄録 |
|
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内容記述タイプ |
Abstract |
|
内容記述 |
This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a <>Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions. |
| 書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E80-A,
号 10,
p. 1826-1833,
発行日 1997-10-20
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| 出版者 |
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|
出版者 |
電子情報通信学会(IEICE) |
| ISSN |
|
|
収録物識別子タイプ |
ISSN |
|
収録物識別子 |
0916-8508 |
| 書誌レコードID |
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|
収録物識別子タイプ |
NCID |
|
収録物識別子 |
AA10826239 |
| 権利 |
|
|
権利情報 |
copyright©1997IEICE |
| 関連サイト |
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識別子タイプ |
URI |
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関連識別子 |
http://www.ieice.org/jpn/trans_online/index.html |
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|
関連名称 |
http://www.ieice.org/jpn/trans_online/index.html |
| フォーマット |
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内容記述タイプ |
Other |
|
内容記述 |
application/pdf |
| 著者版フラグ |
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|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
E80-A_10 _1826.pdf (1.0 MB)
