Item type |
学術雑誌論文 / Journal Article(1) |
公開日 |
2023-02-28 |
タイトル |
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タイトル |
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG |
言語 |
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言語 |
eng |
キーワード |
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主題 |
test generation |
キーワード |
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主題 |
acyclic sequential circuits |
キーワード |
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主題 |
stuck-at fault |
キーワード |
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主題 |
partial scan |
キーワード |
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主題 |
multiple fault |
資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
著者 |
ICHIHARA, Hideyuki
INOUE, Tomoo
市原, 英行
井上, 智生
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抄録 |
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内容記述タイプ |
Abstract |
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内容記述 |
A test generation method with time-expansion model can achieve high fault efficiency for acyclic sequential circuits, which can be obtained by partial scan design. This method, however, requires combinational test pattern generation algorithm that can deal with multiple stuck-at faults, even if the target faults are single stuck-at faults. In this paper, we propose a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just combinational test pattern generation algorithm for single stuck-at faults. Experimental results show that test sequences for acyclic sequential circuits with high fault efficiency are generated in small computational effort. |
書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E86-A,
号 12,
p. 3072-3078,
発行日 2003-12-01
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出版者 |
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出版者 |
電子情報通信学会(IEICE) |
ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
0916-8508 |
権利 |
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権利情報 |
copyright©2003IEICE |
関連サイト |
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識別子タイプ |
URI |
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関連識別子 |
http://www.ieice.org/jpn/trans_online/index.html |
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関連名称 |
http://www.ieice.org/jpn/trans_online/index.html |
フォーマット |
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内容記述タイプ |
Other |
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内容記述 |
application/pdf |
著者版フラグ |
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出版タイプ |
VoR |
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出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |