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ASAver.1: An FPGA-Based Education Board for Computer Architecture/System Design OCHI, Hiroyuki オチ, ヒロユキ KAMIDOI, Yoko カミドイ, ヨウコ KAWABATA, Hideyuki カワバタ, ヒデユキ 上土井, 陽子 川端, 英之 copyright©1997IEICE education of computer architecture system design DLX-like pipelined RISC processor field-programmable gate array verilog-HDL application/pdf This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a <>Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions. 電子情報通信学会(IEICE) 1997-10-20 eng journal article VoR https://hiroshima-cu.repo.nii.ac.jp/records/1298 http://www.ieice.org/jpn/trans_online/index.html http://www.ieice.org/jpn/trans_online/index.html AA10826239 0916-8508 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E80-A 10 1826 1833 https://hiroshima-cu.repo.nii.ac.jp/record/1298/files/E80-A_10 _1826.pdf application/pdf 1.0 MB 2023-02-28